Methods and systems for reducing crosstalk for sets of lines

ABSTRACT

At least one example embodiment discloses a method including determining a first set of lines and a second set of lines in a system, obtaining signals to be transmitted over, or received from, the first set of lines and the second set of lines, obtaining normal operation interval (NOI) vectoring coefficients for the second set of lines, determining discontinuous operation interval (DOI) vectoring coefficients for the first set of lines, the DOI vectoring coefficients for the first set of lines and the NOI vectoring coefficients for the second set of lines being part of a vectoring matrix and jointly processing the signals for a discontinuous operation interval using the vectoring matrix.

BACKGROUND

Performance of a digital subscriber line (DSL) in terms of capacitydepends on a number of factors such as attenuation and a noiseenvironment. Performance of a DSL transmission system is impacted bycrosstalk interference from one twisted line pair to another twistedline pair with the same binder and, to a lesser extent, twisted linepairs in neighboring binders.

Consequently, crosstalk interference may affect data rates across anumber of twisted pair lines.

For instance two communication lines are collocated next to each otherinduce a signal in each other. Due to the induced crosstalk and noisefrom other sources in the surroundings of the communication line, thedata transported on these lines may be affected or corrupted by thecrosstalk and noise. By reducing the crosstalk induced on acommunication line or compensating the crosstalk induced on acommunication line, the amount of corrupted data may be reduced and therate at which information can be reliably communicated is increased.

G.vector uses mutually orthogonal pilots and correlation as described in“Self-FEXT cancellation (vectoring) for use with VDSL2 transceivers,”Series G: Transmission Systems and Media, Digital Systems and Networks,ITU G.993.5, April 2010, the entire contents of which is incorporated byreference.

In the context of providing data network access to homes and businesses,various technologies collectively known as FTTx have been used orproposed. In these technologies, data is conveyed from a networkoperator to an intermediate location using fiber optics, and data isconveyed from the intermediate location to the customer location usingDSL transmission over twisted pair copper lines. The term FTTdp refersto a scenario in which the intermediate location is a “distributionpoint”, serving up to a few dozen customers within a distance of lessthan 200 m. For example, G.fast is a transmission technology that usestime division duplexing (TDD) to duplex downstream and upstreamtransmission.

SUMMARY

At least one example embodiment discloses a method including determininga first set of lines and a second set of lines in a system, obtainingsignals to be transmitted over, or received from, the first set of linesand the second set of lines, obtaining normal operation interval (NOI)vectoring coefficients for the second set of lines, determiningdiscontinuous operation interval (DOI) vectoring coefficients for thefirst set of lines, the DOI vectoring coefficients for the first set oflines and the NOI vectoring coefficients for the second set of linesbeing part of a vectoring matrix and jointly processing the signals fora discontinuous operation interval using the vectoring matrix.

In an example embodiment, the vectoring matrix includes a |B|×(|B|+|A|)submatrix for the discontinuous operation interval, where |B| is anumber of the first set of lines corresponding to the DOI vectoringcoefficients and |A| is a number of the second set of linescorresponding to the NOI vectoring coefficients. In an exampleembodiment, the method further includes storing the |B|×(|B|+|A|)submatrix in a memory storage medium.

In an example embodiment, the first set of lines is associated with ahigher vectoring performance than the second set of lines.

In an example embodiment, the determining determines the first andsecond sets of lines based on at least one of a traffic load of thesystem and static data rate values associated with the lines in thefirst and second sets of lines, respectively.

In an example embodiment, the NOI vectoring coefficients and the DOIvectoring coefficients are precoder coefficients and the vectoringmatrix is a precoding matrix.

In an example embodiment, the NOI vectoring coefficients and the DOIvectoring coefficients are postcoder coefficients and the vectoringmatrix is a postcoding matrix.

In an example embodiment, the postcoding matrix includes a (|B|+|A|)×|B|submatrix for the discontinuous operation interval, where |B| is anumber of the first set of lines corresponding to the DOI postcodercoefficients and |A| is a number of the second set of linescorresponding to the NOI postcoder coefficients.

In an example embodiment, the method further includes storing the(|B|+|A|)×|B| submatrix in a memory storage medium.

At least one example embodiment discloses a method including determininga first set of lines and a second set of lines in a system, obtainingsignals to be transmitted over, or received from, the first set of linesand the second set of lines, determining a first vectoring matrix forthe first set of lines and the second set of lines, the first vectoringmatrix including an identity matrix and a |B|×|B| inverse channelmatrix, where |B| is a number of the first set of lines, determining asecond vectoring matrix, the second vectoring matrix including normaloperation interval (NOI) vectoring coefficients associated with thefirst set of lines and the second set of lines and an identity matrixand jointly processing the signals for a discontinuous operationinterval by sequentially applying the first matrix and the secondmatrix.

In an example embodiment, the jointly processing jointly processes thesignals by sequentially applying the second matrix followed by the firstmatrix.

In an example embodiment, the jointly processing jointly processes thesignals by sequentially applying the first matrix followed by the secondmatrix.

In an example embodiment, the first set of lines is associated with ahigher vectoring performance than the second set of lines.

At least one example embodiment discloses an access node including aprocessor configured to determine a first set of lines and a second setof lines in a system, obtain signals to be transmitted over, or receivedfrom, the first set of lines and the second set of lines, obtain normaloperation interval (NOI) vectoring coefficients for the second set oflines, determine discontinuous operation interval (DOI) vectoringcoefficients for the first set of lines, the DOI vectoring coefficientsfor the first set of lines and the NOI vectoring coefficients for thesecond set of lines being part of a vectoring matrix and jointly processthe signals for a discontinuous operation interval using the vectoringmatrix.

In an example embodiment, the vectoring matrix includes a |B|×(|B|+|A|)submatrix for the discontinuous operation interval, where |B| is anumber of the first set of lines corresponding to the DOI vectoringcoefficients and |A| is a number of the second set of linescorresponding to the NOI vectoring coefficients.

In an example embodiment, the processor is configured to store the|B|×(|B|+|A|) submatrix in a memory storage medium.

In an example embodiment, the first set of lines is associated with ahigher vectoring performance than the second set of lines.

In an example embodiment, the processor is configured to determine thefirst and second sets of lines based on at least one of a traffic loadof the system and static data rate values associated with the lines inthe first and second sets of lines, respectively.

In an example embodiment, the NOI vectoring coefficients and the DOIvectoring coefficients are precoder coefficients and the vectoringmatrix is a precoding matrix.

In an example embodiment, the NOI vectoring coefficients and the DOIvectoring coefficients are postcoder coefficients and the vectoringmatrix is a postcoding matrix.

In an example embodiment, the postcoding matrix includes a (|B|+|A|)×|B|submatrix for the discontinuous operation interval, where |B| is anumber of the first set of lines corresponding to the DOI postcodercoefficients and |A| is a number of the second set of linescorresponding to the NOI postcoder coefficients.

In an example embodiment, the processor is configured to store the(|B|+|A|)×|B| submatrix in a memory storage medium.

At least one example embodiment discloses an access node including aprocessor configured to determine a first set of lines and a second setof lines in a system, obtain signals to be transmitted over, or receivedfrom, the first set of lines and the second set of lines, determine afirst vectoring matrix for the first set of lines and the second set oflines, the first vectoring matrix including an identity matrix and a|B|×|B| inverse channel matrix, where |B| is a number of the first setof lines, determine a second vectoring matrix, the second vectoringmatrix including normal operation interval (NOI) vectoring coefficientsassociated with the first set of lines and the second set of lines andan identity matrix and jointly process the signals for a discontinuousoperation interval by sequentially applying the first matrix and thesecond matrix.

In an example embodiment, the processor is configured to jointly processthe signals by sequentially applying the second matrix followed by thefirst matrix.

In an example embodiment, the processor is configured to jointly processthe signals by sequentially applying the first matrix followed by thesecond matrix.

BRIEF DESCRIPTION OF THE DRAWINGS

Example embodiments will become more appreciable through the descriptionof the drawings, which are not limiting of example embodiments, inwhich:

FIG. 1 illustrates a communication network according to an exampleembodiment;

FIG. 2 illustrates a portion of a controller including a precoderaccording to an example embodiment;

FIG. 3A illustrates a method of transmitting using block boosting on adownstream according to an example embodiment;

FIG. 3B illustrates a method of transmitting using sequential boostingon the downstream according to an example embodiment;

FIG. 4 illustrates a portion of the controller including a postcoderaccording to an example embodiment;

FIG. 5A illustrates a method of using block boosting on an upstreamaccording to an example embodiment; and

FIG. 5B illustrates a method of using sequential boosting on theupstream according to an example embodiment.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

Various example embodiments will now be described more fully withreference to the accompanying drawings in which some example embodimentsare shown.

While example embodiments are capable of various modifications andalternative forms, the embodiments are shown by way of example in thedrawings and will be described herein in detail. It should beunderstood, however, that there is no intent to limit exampleembodiments to the particular forms disclosed. On the contrary, exampleembodiments are to cover all modifications, equivalents, andalternatives falling within the scope of this disclosure. Like numbersrefer to like elements throughout the description of the figures.

Although the terms first, second, etc. may be used herein to describevarious elements, these elements should not be limited by these terms.These terms are only used to distinguish one element from another. Forexample, a first element could be termed a second element, andsimilarly, a second element could be termed a first element, withoutdeparting from the scope of this disclosure. As used herein, the term“and/or,” includes any and all combinations of one or more of theassociated listed items.

When an element is referred to as being “connected,” or “coupled,” toanother element, it can be directly connected or coupled to the otherelement or intervening elements may be present. By contrast, when anelement is referred to as being “directly connected,” or “directlycoupled,” to another element, there are no intervening elements present.Other words used to describe the relationship between elements should beinterpreted in a like fashion (e.g., “between,” versus “directlybetween,” “adjacent,” versus “directly adjacent,” etc.).

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting. As used herein, thesingular forms “a,” “an,” and “the,” are intended to include the pluralforms as well, unless the context clearly indicates otherwise. It willbe further understood that the terms “comprises,” “comprising,”“includes,” and/or “including,” when used herein, specify the presenceof stated features, integers, steps, operations, elements, and/orcomponents, but do not preclude the presence or addition of one or moreother features, integers, steps, operations, elements, components,and/or groups thereof.

It should also be noted that in some alternative implementations, thefunctions/acts noted may occur out of the order noted in the figures.For example, two figures shown in succession may in fact be executedsubstantially concurrently or may sometimes be executed in the reverseorder, depending upon the functionality/acts involved.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which example embodiments belong. Itwill be further understood that terms, e.g., those defined in commonlyused dictionaries, should be interpreted as having a meaning that isconsistent with their meaning in the context of the relevant art andwill not be interpreted in an idealized or overly formal sense unlessexpressly so defined herein.

Portions of example embodiments and corresponding detailed descriptionare presented in terms of algorithms performed by a controller. Analgorithm, as the term is used here, and as it is used generally, isconceived to be a self-consistent sequence of steps leading to a desiredresult. The steps are those requiring physical manipulations of physicalquantities. Usually, though not necessarily, these quantities take theform of optical, electrical, or magnetic signals capable of beingstored, transferred, combined, compared, and otherwise manipulated. Ithas proven convenient at times, principally for reasons of common usage,to refer to these signals as bits, values, elements, symbols,characters, terms, numbers, or the like.

Specific details are provided in the following description to provide athorough understanding of example embodiments. However, it will beunderstood by one of ordinary skill in the art that example embodimentsmay be practiced without these specific details. For example, systemsmay be shown in block diagrams so as not to obscure the exampleembodiments in unnecessary detail. In other instances, well-knownprocesses, structures and techniques may be shown without unnecessarydetail in order to avoid obscuring example embodiments.

In the following description, illustrative embodiments will be describedwith reference to acts and symbolic representations of operations (e.g.,in the form of flow charts, flow diagrams, data flow diagrams, structurediagrams, block diagrams, etc.) that may be implemented as programmodules or functional processes include routines, programs, objects,components, data structures, etc., that perform particular tasks orimplement particular abstract data types and may be implemented usingexisting hardware at existing network elements, existing end-userdevices and/or post-processing tools (e.g., mobile devices, laptopcomputers, desktop computers, etc.). Such existing hardware may includeone or more Central Processing Units (CPUs), digital signal processors(DSPs), application-specific-integrated-circuits, field programmablegate arrays (FPGAs) computers or the like.

Unless specifically stated otherwise, or as is apparent from thediscussion, terms such as “processing” or “computing” or “calculating”or “determining” or “displaying” or the like, refer to the action andprocesses of a computer system, or similar electronic computing device,that manipulates and transforms data represented as physical, electronicquantities within the computer system's registers and memories intoother data similarly represented as physical quantities within thecomputer system memories or registers or other such information storage,transmission or display devices.

Although a flow chart may describe the operations as a sequentialprocess, many of the operations may be performed in parallel,concurrently or simultaneously. In addition, the order of the operationsmay be re-arranged. A process may be terminated when its operations arecompleted, but may also have additional steps not included in thefigure. A process may correspond to a method, function, procedure,subroutine, subprogram, etc. When a process corresponds to a function,its termination may correspond to a return of the function to thecalling function or the main function.

Note also that the software implemented aspects of example embodimentsare typically encoded on some form of tangible (or recording) storagemedium or implemented over some type of transmission medium. Asdisclosed herein, the term “storage medium” may represent one or moredevices for storing data, including read only memory (ROM), randomaccess memory (RAM), magnetic RAM, magnetic disk storage mediums,optical storage mediums, flash memory devices and/or other tangiblemachine readable mediums for storing information. The term“computer-readable medium” may include, but is not limited to, portableor fixed storage devices, optical storage devices, and various othermediums capable of storing, containing or carrying instruction(s) and/ordata.

Furthermore, example embodiments may be implemented by hardware,software, firmware, middleware, microcode, hardware descriptionlanguages, or any combination thereof. When implemented in software,firmware, middleware or microcode, the program code or code segments toperform the necessary tasks may be stored in a machine or computerreadable medium such as a computer readable storage medium. Whenimplemented in software, a processor or processors will perform thenecessary tasks.

A code segment may represent a procedure, function, subprogram, program,routine, subroutine, module, software package, class, or any combinationof instructions, data structures or program statements. A code segmentmay be coupled to another code segment or a hardware circuit by passingand/or receiving information, data, arguments, parameters or memorycontents. Information, arguments, parameters, data, etc. may be passed,forwarded, or transmitted via any suitable means including memorysharing, message passing, token passing, network transmission, etc.

Example embodiments may be implemented over the twisted pair section ofan FTTdp network, but are not limited thereto.

Both postcoding and precoding operations will be described. The terms“joint-processing” and “vectoring” cover both precoding and postcodingoperations.

G.fast is a transmission technology that uses time division duplexing(TDD) to duplex downstream and upstream transmission. TDD frames areused as data units, where each TDD frame consists of a separatedownstream and upstream time interval. Each interval on its own isfurther divided into a normal operation interval (NOI) during which alllines are allowed to transmit data (typically vectored), and adiscontinuous operation interval (DOI) during which only a subset oflines are allowed to transmit data, while the remaining lines arediscontinued (quiet). Thus, discontinuing lines reduces powerconsumption of the system.

Discontinuous vectoring refers to applying vectoring to the active linesin DOI. A symbol in NOI can in principle be a data symbol or an idlesymbol. In DOI, a line that is scheduled for transmission can transmit adata symbol, an idle symbol or a quiet symbol. However, a line that isnot scheduled for transmission in DOI, should be a quiet symbol.

Switching subsets of lines in G.fast employs time division duplexing fordynamic resource allocation (DRA). Switching OFF refers to switching apart of the analog front end and/or digital logic to a reduced powerconsumption level.

Two classes of conventional discontinuous vectoring schemes can beapproximate methods and exact methods. The approximate methods work withrelatively low complexity but also with relative poor SNR performancewhereas exact methods achieve high SNR performance but have highimplementation complexity.

Two approximate methods are a virtual precoder input method (VPI) methodand a muted vectoring (MV) method. When using VPI and MV, the only wayto obtain ideal data rate performance for a given interval of time is toturn off DOI and use NOI exclusively for that period of time.

A block time division multiple access (TDMA) computes multiple DOIprecoder blocks, but only one DOI precoder block is active at a time. Inblock TDMA, a certain number of subsets of lines are chosen in advance,and DOI precoder blocks are computed for each subset.

In operation, a DRA module selects which subset is to be active duringeach time slot. For the block TDMA scheme to ensure full vectoring datarate performance for a premium set of lines at all times, each subsetincludes the set of premium lines. In this way, the premium lines can beactive in each time slot if needed, and achieve ideal SNR performance.However, a relatively large amount of memory is used to store theprecoder coefficients associated with each subset.

For a system with N lines and considering n block DOI precoders of sizesM₁, M₂, . . . , M_(n) (with M_(i)>=|B|, for all i), this requires anadditional DOI memory of M₁×M₁+M₂×M₂+ . . . +M_(n)×M_(n), next to thealready provisioned NOI memory, where |B| is the number of premiumlines. On the computational side, matrix inverses are updated wheneverthe subsets change. For example, to remove a line from a subset withM_(i) lines, updating the precoder matrix uses about M_(i) ² operations.To add a line to an existing subset, updating the precoder matrix usesabout 6 M_(i) ² operations.

To solve/reduce these issues, example embodiments disclose adiscontinuous blocking vectoring scheme with different service users ata full vectoring data rate.

More specifically, example embodiments provide full vectoring data rateperformance for at least a subset of lines at all moments, even whenusing discontinuous vectoring to save power consumption. For example, asubset of lines is subscribed to some premium service subscription forwhich full vectoring data rate performance is used at all moments, evenwhen using discontinuous mode (for the other lines) to save power. Inanother example, long lines may already have a small data rate and onewants to prevent further reduction of these data rates when usingdiscontinuous vectoring.

FIG. 1 illustrates a communication system according to an exampleembodiment. As shown in FIG. 1, the system 500 includes a distributionpoint or access node 100 and Customer Premises Equipment (CPEs) 200-1 to200-m, where m may be an integer greater than 1.

The access node 100 may be under control of an operator. The access node100 includes an optical network unit (ONU) 115 configured to communicatewith a network processor (NP) 120. As is known, the ONU 115 provides ahigh-bandwidth data connection over a fiber optic channel to an opticalline terminal (OLT) located in a central office. The ONU 115 passesreceived downstream data frames or packets to the NP 120, which thendetermines the destination for the frames or packets and accordinglyforwards them to an appropriate interface (e.g., DSL, ADSL, G.fast, etc.interface). Similarly, in the upstream direction, the NP 120 forwardsframes or packets from the interfaces to the ONU 115.

The NP 120 provides signals to processing devices 125-1 to 125-m. Theprocessing devices 125 are configured for point-to-point communication.

The access node 100 further includes a controller 130. The controller130 is configured to receive signal data collectively referred to as asignal vector from the processing devices 125. The signal data mayinclude signal values intended to be received by correspondingprocessing devices 260-1 to 260-m in the CPEs 200. In the downstreamdirection, the controller 130 is also configured to precode the signalvector, and send the resulting data back to the processing devices 125for transmission to the CPEs 200. The processing devices 125 then sendthe precoded signal data over respective lines 300 via respective analogfront ends (AFEs) 135-1 to 135-m. In the upstream direction, theprocessing devices 125 receive crosstalk-contaminated signals from theAFEs 135. The controller 130 receives the crosstalk-contaminated signals(collectively referred to as received signal vector) from the processingdevices 125, postcodes the received signal vector, and provides theprocessing devices 125 with the post-compensated signal data. Theprocessing devices 125 then continue to process the signal data todemodulate the intended upstream information.

Generally, the data exchanged between processing devices would befrequency-domain samples, but alternatively the data could berepresented as time-domain samples, for example.

As discussed above, the controller 130 communicates with the processingdevices 125. Alternatively, the controller 130 may be between theprocessing devices 125 and the respective AFEs 135-1 to 135-m. Thus, thelocation of the controller 130 is not limited to the location shown inFIG. 1.

Furthermore, it will be understood that the access node 100 may includea memory 140, or multiple memories. The NP 120, the controller 130,and/or the processing devices 125 execute programs and/or programmodules stored on the memory 140 to perform their respective functionsand the functions of the access node 100. The operation of the accessnode 100 will be described in greater detail below with respect to someexample embodiments. The memories may be external to and/or internal tothe NP 120, the controller 130, and/or the processing devices 125. Forthe purposes of simplicity of illustration only, only the memory 140associated with the controller 130 is shown.

As discussed above, each of the processing devices 125 may communicatewith a respective one of the CPEs 200 over the communication lines 300through an associated AFE 135. The lines 300 (also referred to as links)may be telephone lines (e.g., twisted copper pairs), and the CPEs 200-1to 200-m may be modems or other interface devices operating according toa communication standard for transmitting data over telephone lines. TheCPEs 200-1 to 200-m may be located in various customer premises. Each ofthe CPEs 200-1 to 200-m includes an AFE 255-1 to 255-m and respectiveprocessing devices 260-1 to 260-m. Each of the AFEs 255-1 to 255-m maybe the same or substantially the same as the AFEs 135-1 to 135-m.

FIG. 2 illustrates a portion of the controller 130 including a precoderaccording to an example embodiment. The controller 130 has acommunication interface 270 with each of the processing devices 125-1 to125-m. The incoming communication interface 270 receives data andcontrol signals from the processing devices 125-1 to 125-m. The incomingcommunication interface 270 forwards symbol data x to the subsetselector 275.

The processing devices 125-1 to 125-m may maintain individual queuescontaining packets of information to be sent on each of the N lines. Atany point in time, some queues may have packets waiting to be sent,while other queues are empty. A dynamic resource allocation (DRA) module272 collects information about the queues from the processing devices125-1 to 125-m. The DRA module 272 then determines which subset of linesis to be active in each time slot. The DRA module 272 determines whichsubset of lines is to be active in each time slot using any knownalgorithm.

The DRA module 272 notifies the subset selector 275 of the subset oflines that will transmit physical layer signals (active lines) and asubset of lines that will not send physical layer signals (discontinuedlines) during a DMT slot t. The active lines may or may not have data tosend. An active line without data to send is called an idle line; in avectored system, all active idle lines send compensation signalsgenerated by the precoder 285, regardless of whether they have data tosend. The incoming communication interface 270 designates the activelines for transmission during a selected time slot.

The incoming communication interface 270 also forwards receiverfeedback, such as crosstalk characteristics to the subset selector 275and to a vectoring control entity (VCE) 280.

The crosstalk characteristics could be error feedback samples or DFToutput samples collected by the receiver, as described in the G.fastrecommendation (the samples are then processed by correlation etc. tocome up with estimates of crosstalk coefficients). Alternatively, thecrosstalk characteristics could be estimates of crosstalk coefficients,computed elsewhere and then forwarded to the VCE. Additionally, thecrosstalk characteristics could be other forms of feedback, e.g., SNRmeasurements, that are affected by crosstalk and can be used to learnsomething about the crosstalk.

The subset selector 275 forwards symbol data x_(s) corresponding to thesubset of active lines to a precoder 285.

The precoder 285 applies coefficients received from the VCE 280 to thesymbol data received from the subset selector 275 to produce compensateddata symbols y_(s) (precoded data), which are forwarded to an outgoingcommunication interface 290. The outgoing communication interface 290sends the compensated data symbols to the processing devices 125-1 to125-m. Additionally, the incoming communication interface 270periodically receives receiver feedback data, which it forwards to theVCE 280.

In FIG. 2, the incoming communication interface 270, the subset selector275, the precoder 285 and the outgoing communication interface 290 maybe considered data path elements while the DRA module 272 and thevectoring control entity 280 may be considered control path elementsthat instruct the data path elements what to do.

Each of the incoming communication interface 270, the subset selector275, the precoder 285, the outgoing communication interface 290, the DRAmodule 272 and the vectoring control entity 280 may be implemented inhardware, a processor configured to execute software, firmware, or anycombination thereof, for example. When at least one of the incomingcommunication interface 270, the subset selector 275, the precoder 285,the outgoing communication interface 290, the DRA module 272 and thevectoring control entity 280 is hardware, such existing hardware mayinclude one or more Central Processing Units (CPUs), digital signalprocessors (DSPs), application-specific-integrated-circuits (ASICs),field programmable gate arrays (FPGAs) or the like configured as specialpurpose machines to perform the functions of the at least one of theincoming communication interface 270, the subset selector 275, theprecoder 285, the outgoing communication interface 290, the DRA module272 and the vectoring control entity 280. CPUs, DSPs, ASICs and FPGAsmay generally be referred to as processors and/or microprocessors.

In the event where at least one of the incoming communication interface270, the subset selector 275, the precoder 285, the outgoingcommunication interface 290, the DRA module 272 and the vectoringcontrol entity 280 is a processor executing software, the processor isconfigured as a special purpose machine to execute the software, storedin a storage medium (e.g., memory 140), to perform the functions of theat least one of the incoming communication interface 270, the subsetselector 275, the precoder 285, the outgoing communication interface290, the DRA module 272 and the vectoring control entity 280. In such anembodiment, the processor may include one or more Central ProcessingUnits (CPUs), digital signal processors (DSPs),application-specific-integrated-circuits (ASICs), field programmablegate arrays (FPGAs) computers.

At least some example embodiments disclose a discontinuous vectoringmethod (pre- or postcoder) where a premium set of lines B are dedicatedfor full vectoring data rate performance during their symboltransmissions. The set of lines B can be static or the controller 130may vary the set of lines B over time (e.g., periodically ordynamically) depending on the traffic load or on operator/systemrequirements (e.g., minimum data rates associated with the lines). Theminimum data rates may be static values and may be associated with aservice of the user. For example, a premium service line would have ahigher associated minimum data rate than a line not associated with thepremium service. In another example, the minimum data rate may be basedon the length of the line.

A non-premium set of lines that can be active (with a better thannon-vectoring performance) or discontinued to save power. Thenon-premium set of lines can be static or the controller 130 may varythe non-premium set of lines over time (e.g., periodically ordynamically) depending on the traffic load or on operator/systemrequirements (e.g., minimum data rates associated with the lines).

Based on estimated channel information and an NOI pre-/postcoder(already available in memory as it is used for vectored NOI operation),one or more DOI pre-/postcoders are generated for discontinuousvectoring obtaining full vectoring data rate performance for the premiumset of lines. In addition, the non-premium set of lines that are activehave a better than non-vectoring performance during DOI. Some of thenon-premium set of lines can be discontinued in DOI (to save power).

Example embodiments save memory by re-using NOI pre-/postcodercoefficients for the non-premium lines in DOI. In this approach,DOI-specific coefficients are stored for the premium lines and not thenon-premium lines.

For example, a precoder/postcoder for a system of N lines, with DOIblock sizes M₁, M₂, . . . , M_(n), only requires DOI memory of totalsize |B|×(M₁+ . . . +M_(n)), compared with the memory size M₁ ²+ . . .+M_(n) ² required for Block TDMA.

Downstream—Block Boosting

In at least some example embodiments, the controller 130 implementsblock boosting for the downstream (precoder).

A (normalized) channel is given by G (with the channel system modelH=diag(H)G, where diag(H) refers to the diagonal matrix containing thediagonal elements of H). The controller 130 determines the channel Gusing any known method such as sending pilot symbols to the CPEs 200-1to 200-m and receiving error feedback from the CPEs 200-1 to 200-m.

The controller 130 determines the set of lines B to be the premium setof lines. As stated above, the set of lines B can be static or canchange dynamically over time depending on, e.g., the variation of thetraffic load or operator/system requirements. The controller 130 thendetermines subsets of non-premium lines A_(k), which are subblocks oflines that can be simultaneously active with the premium set of lines B.The entire block is denoted M_(k)=B∪A_(k).

The controller 130 may determine the subsets of non-premium lines A_(k)in various ways to group the subsets of non-premium lines A_(k)according to minimum data rates associated with the lines and/or trafficload.

For example, there may be 32 lines, and 4 lines are premium lines, inthe set B. The controller 130 may define A₁ as the top 4 non-premiumlines in terms of traffic load, and overlapping set A₂ as the top 12non-premium lines in terms of traffic load. Then, the controller 130uses the NOI (all 32 lines active) for enough symbols to meet the needsof the lines not in A₂. The controller 130 will then have set M₂=B u A₂(16 lines) active for enough symbols to meet any additional needs oflines in A₂ but not in A₁. The controller 130 will then have set M₁=B∪A₁(8 lines) active for enough symbols to meet any additional needs oflines in A₁ but not in B. Finally, the controller 130 will then set M₀=B(4 lines) active for enough symbols to meet any additional needs of thepremium lines B.

The sets A_(k) could also be modified by the controller 130 to take intoaccount crosstalk coupling strength, as described in U.S. applicationSer. No. 14/562,197, filed on Dec. 5, 2014, the entire contents of whichare hereby incorporated by reference. For example, a line that would nota priori be in A₂ because it has a low traffic level could be added toA₂ because it has a strong coupling with other lines in A₂, andincluding it will improve the rate of other lines when M₂ is active.

For each subblock A_(k), the full channel G and a precoder matrixP_(Down) can be written as follows:

$G = \begin{bmatrix}G_{DD} & G_{{DA}_{k}} & G_{DB} \\G_{A_{k}D} & G_{A_{k}A_{k}} & G_{A_{k}B} \\G_{BD} & G_{{BA}_{k}} & G_{BB}\end{bmatrix}$ ${P_{Down} = \begin{bmatrix}P_{{Down}\mspace{14mu} {DD}} & P_{{Down}\mspace{14mu} {DA}_{k}} & P_{{Down}\mspace{14mu} {DB}} \\P_{{Down}\mspace{14mu} A_{k}D} & P_{{Down}\mspace{14mu} A_{k}A_{k}} & P_{{Down}\mspace{14mu} A_{k}B} \\P_{{Down}\mspace{14mu} {BD}} & P_{{Down}\mspace{14mu} {BA}_{k}} & P_{{Down}\mspace{14mu} {BB}}\end{bmatrix}},$

where D is a set of discontinued lines, A_(k) is the set of non-premiumlines in subblock k, and B is the set of premium lines. A zero-forcingprecoder (without discontinued lines) satisfies:

GP _(Down) =I

The subscript “Down” is used to identify a matrix used to removecrosstalk on the downstream. Moreover, while a zero-forcing precoder isdiscussed, it should be understood that precoders other than azero-forcing precoder may be used.

With block boosting, the controller 130 uses the following precodercoefficients in DOI when the set of lines {A_(k), B} are active:

$\begin{bmatrix}P_{{Down}\mspace{14mu} A_{k}A_{k}} & P_{{Down}\mspace{14mu} A_{k}B} \\{G_{BB}^{- 1}G_{{BA}_{k}}P_{{Down}\mspace{14mu} A_{k}A_{k}}} & {G_{BB}^{- 1}\left( {I - {G_{{BA}_{k}}P_{{Down}\mspace{14mu} A_{k}B}}} \right)}\end{bmatrix},$

The coefficients P_(DownAkAk) and P_(DownAkB) are used for vectoring thenon-premium lines in the subblock A_(k) and are the same coefficientsused in NOI in the downstream. Therefore, the coefficients P_(DownAkAk)and P_(DownAkB) do not require any additional memory because they arealready stored in the memory 140 for NOI in the downstream. Using thecoefficients P_(DownAkAk) and P_(DownAkB) results in a partiallyvectored rate for lines in subblock A_(k).

The remaining coefficients G_(BB) ⁻¹G_(BA) _(k) P_(Down A) _(k) _(A)_(k) and G_(BB) ⁻¹(I−G_(BA) _(k) P_(Down A) _(k) _(B)) are specific tosubblock A_(k) and are computed by the controller 130 to ensure that thelines in the set of lines B achieve full signal-to-noise ratio (SNR)performance. The VCE 280 determines coefficients G_(BB) ⁻¹G_(BA) _(k)P_(Down A) _(k) _(A) _(k) and G_(BB) ⁻¹(I−G_(BA) _(k) P_(Down A) _(k)_(B)) using knowledge of G (estimated and stored in the VCE 280) and ofP_(Down) (a copy of which is also stored in the VCE 280).

In particular, during DOI using the combination {A_(k),B}, the resultingchannel after precoding is

$\begin{matrix}{{{GP}_{Down}\lbrack k\rbrack} = \begin{bmatrix}G_{DD} & G_{{DA}_{k}} & G_{DB} \\G_{A_{k}D} & G_{A_{k}A_{k}} & G_{A_{k}B} \\G_{BD} & G_{{BA}_{k}} & G_{BB}\end{bmatrix}} \\{\begin{bmatrix}0 & 0 & 0 \\0 & P_{{Down}\mspace{14mu} A_{k}A_{k}} & P_{{Down}\mspace{14mu} A_{k}B} \\0 & {{- G_{BB}^{- 1}}G_{{BA}_{k}}P_{{Down}\mspace{14mu} A_{k}A_{k}}} & {G_{BB}^{- 1}\left( {I - {G_{{BA}_{k}}P_{{Down}\mspace{14mu} A_{k}B}}} \right)}\end{bmatrix}} \\{= \begin{bmatrix}0 & {G_{{DA}_{k}} + X_{2}} & {G_{DB} + X_{2}} \\0 & {I + X_{2}} & X_{2} \\0 & 0 & I\end{bmatrix}}\end{matrix}$

where X₂ is a matrix subblock indicating second order crosstalk terms(e.g., terms generated from the product of off-diagonal crosstalkelements) and D represents a set of lines that are not active during thespecified DOI interval, i.e., the set of lines not in B or A_(k).

There are no residual X₂ terms in the rows corresponding to the set ofpremium lines B. As a result, the set of premium lines B get fullvectored performance. The presence of the residual X₂ terms in the rowscorresponding to the set of lines A_(k) means that the set of linesA_(k) get “partially vectored” performance (better than non-vectored),with first crosstalk terms removed, but second-order terms remaining.

As described, the controller 130 may perform at least two tasks. First,the controller 130 (e.g., the VCE 280) determines the subblocks {B,A₁},{B,A₂}, . . . , {B,A_(n)} for which the controller 130 will storeprecoding coefficients in the memory 140. This includes determining howmany subblocks and which lines to include in the subblocks. Thecontroller 130 may determine the subblocks based on traffic loadestimations/requirements (over a longer period), which may be updated.For example, the controller 130 determines the subblocks to achieve adesired energy-throughput objective trade-off.

Second, the controller 130 determines which subblocks to apply duringwhich symbols in the DOI. The controller 130 may determine whichsubblocks to apply during which symbols in the DOI based oninstantaneous traffic load requirements, where the schedule is updatedat a typically much faster pace than the subblock determination.

The following description illustrates how memory is saved. P_(Down)[−1]is an NOI precoder and P_(Down)[k] is a precoder in use when {B,A_(k)}is active. P_(Down)[0] is a precoder in use when the subset B is active.Since

P _(DownAkAk) [k]=P _(DownAkAk)[−1], and

P _(DownAkB) [k]=P _(DownAkB)[−1],

the controller 130 and the memory 140 do not use any additional storagebeyond Down P_(Down)[−1] for the P_(DownAkAk)[k] and P_(DownAkB)[k]submatrices of P_(Down)[k].

The controller 130 (e.g., the VCE 280) computes and stores

P _(DownBA) _(k) [k]=G _(BB) ⁻¹ G _(BA) _(k) P _(DownA) _(k) _(A) _(k)[−1], and

P _(DownBB) [k]=G _(BB) ⁻¹(I−G _(BA) _(k) P _(DownA) _(k) _(B)[−1])

which are |B|×|A_(k)| and |B|×|B| matrices, respectively. By contrast,for block TDMA, the controller 130 would have to store the entire(|B|+|A_(k)|)×(|B|+|A_(k)|) matrix P_(Down)[k].

The controller 130 may store the |B|×|B| matrix

P _(DownBB)[0]=G _(BB) ⁻¹

for when only the premium lines B are active.

Consequently, while matrix inverses of size (|A_(k)|+|B|)×(|A_(k)|+|B|)must be computed for block TDMA, the controller 130 only has to computea |B|×|B| matrix inverse (G_(BB) ⁻¹) when implementing block boostingfor the downstream.

FIG. 3A illustrates a method of transmitting using block boosting on thedownstream. The method of FIG. 3A may be performed by the access node100. More specifically, the controller 130 may perform steps S300-S315.

At S300, the access node determines a first set of lines and a secondset of lines. The first set of lines may be the set of lines B and thesecond set of lines may be the set of lines A_(k).

At S305, the controller 130 obtains NOI precoder coefficients for thesecond set of lines. For example, the controller 130 obtains thecoefficients P_(DownAkAk)[−1] and P_(DownAkB)[−1] used in NOI for thedownstream from the memory 140.

At S310, the controller 130 determines DOI precoder coefficients for thefirst set of lines. The DOI precoder coefficients for the first set oflines and the NOI precoder coefficients for the second set of lines formpart of a precoding matrix.

At S315, the controller 130 precodes a signal for a discontinuousoperation interval using the precoding matrix. At S320, the access node100 transmits over the first and second sets of lines based on theprecoded signal.

Downstream—Sequential Boosting

As an alternative to block boosting, the controller 130 may implementsequential boosting for the downstream (precoder), in at least someexample embodiments.

When using sequential boosting for the downstream, the controller 130sequentially applies two sparse matrices as follows:

${\begin{bmatrix}0 & 0 & 0 \\0 & I & 0 \\{{- G_{BB}^{- 1}}G_{BD}} & {{- G_{BB}^{- 1}}G_{BA}} & G_{BB}^{- 1}\end{bmatrix}\begin{bmatrix}0 & 0 & 0 \\0 & P_{{Down}\mspace{14mu} {AA}} & P_{{Down}\mspace{14mu} {AB}} \\0 & 0 & I\end{bmatrix}},$

where A refers to active non-premium lines, B to the premium lines and Idenotes an identity matrix.

The controller 130 may not identify the subblock A in advance, but anylines outside the premium set of lines B can discontinue at any timeslot. The remaining non-premium lines that are not discontinued mayconstitute the subblock A. The computations performed by the controller130 are sequential, meaning that the results of the first matrixmultiplication (matrix with the P_(Down) terms) must be calculated andavailable before beginning the second matrix multiplication (the matrixwith the G and G⁻¹ terms).

FIG. 3B illustrates a method of transmitting using sequential boostingon the downstream. The method of FIG. 3B may be performed by the accessnode 100. More specifically, the controller 130 may perform stepsS350-S370.

At S350, the controller 130 determines a first matrix for precodingtransmission from an access node to a plurality of downstream devicesover a plurality of lines. The plurality of lines includes first linesand second lines. The first lines are associated with a higher vectoringperformance than the second set of lines. The first matrix includes anidentity matrix and a |B|×|B| inverse channel submatrix G_(BB) ⁻¹, where|B| is the number of first lines. The first matrix also includes −G_(BB)⁻¹G_(BD) and −G_(BB) ⁻¹G_(BA) submatrices.

At S360, the controller 130 determines a second matrix for precoding thetransmission. The second matrix includes normal operation interval (NOI)precoding coefficients associated with the first and second lines and anidentity matrix. At S370, the controller 130 precodes a signal bysequentially applying the second matrix followed by the first matrix tothe signal.

Upstream

While the above described embodiments are described with reference todetermining precoder coefficients, it should be understood that similarmethods may be applied to determine postcoder coefficients.

For example, FIG. 4 illustrates a portion of the controller 130 forprocessing upstream communications. As shown, the controller 130 has acommunication interface 405 to receive symbol data from the CPEs200-1-200-m. The communication interface 405 forwards the symbol data toa postcoder 410. The postcoder 410 applies a postcoder matrix to obtainpost-coded symbol data. An outgoing communication interface 415 forwardsthe post-coded symbol data to the respective processing devices125-1-125-m.

As described above, the VCE 280 is configured to store to and retrievedata from the memory (storage medium) 140, such as savedprecoding/postcoding matrices.

Each of the communication interface 405 and the postcoder 410 may beimplemented in hardware, a processor configured to execute software,firmware, or any combination thereof, for example. When at least one ofthe communication interface 405 and the postcoder 410 is hardware, suchexisting hardware may include one or more Central Processing Units(CPUs), digital signal processors (DSPs),application-specific-integrated-circuits (ASICs), field programmablegate arrays (FPGAs) or the like configured as special purpose machinesto perform the functions of the at least one of the communicationinterface 405 and the postcoder 410. CPUs, DSPs, ASICs and FPGAs maygenerally be referred to as processors and/or microprocessors.

In the event where at least one of the communication interface 405 andthe postcoder 410 is a processor executing software, the processor isconfigured as a special purpose machine to execute the software, storedin a storage medium (e.g., memory 140), to perform the functions of theat least one of the communication interface 405 and the postcoder 410.In such an embodiment, the processor may include one or more CentralProcessing Units (CPUs), digital signal processors (DSPs),application-specific-integrated-circuits (ASICs), field programmablegate arrays (FPGAs) computers.

Upstream—Block Boosting

Suppose the (normalized) channel is given by G (with the channel systemmodel H=Gdiag(H), where diag(H) refers to a diagonal matrix containingthe diagonal elements of H). For each subblock A_(k), the full channel Gand the postcoder P_(Up) can be written as follows:

$G = \begin{bmatrix}G_{DD} & G_{{DA}_{k}} & G_{DB} \\G_{A_{k}D} & G_{A_{k}A_{k}} & G_{A_{k}B} \\G_{BD} & G_{{BA}_{k}} & G_{BB}\end{bmatrix}$ ${P_{Up} = \begin{bmatrix}P_{{Up}_{DD}} & P_{{Up}_{{DA}_{k}}\mspace{14mu}} & P_{{Up}_{DB}} \\P_{{Up}_{A_{k}D}} & P_{{Up}_{A_{k}A_{k}}} & P_{{Up}_{A_{k}B}} \\P_{{Up}_{BD}} & P_{{Up}_{{BA}_{k}}} & P_{{Up}_{BB}}\end{bmatrix}},$

where a zero-forcing postcoder satisfies:

P _(Up) G=I

The subscript “UP” is used to identify a matrix used to remove crosstalkon the upstream.

Moreover, while a zero-forcing postcoder is discussed, it should beunderstood that postcoders other than a zero-forcing postcoder may beused.

In an example embodiment, the controller 130 uses the followingpostcoder coefficients in DOI when the set of lines {A_(k), B} areactive:

$\begin{bmatrix}P_{{Up}_{A_{k}A_{k}}} & P_{{Up}_{A_{k}B}} \\{{- \left( {G_{BB} - {G_{{BA}_{k}}G_{A_{k}A_{k}}^{- 1}G_{A_{k}B}}} \right)^{- 1}}G_{{BA}_{k}}G_{A_{k}A_{k}}^{- 1}} & \left( {G_{BB} - {G_{{BA}_{k}}G_{A_{k}A_{k}}^{- 1}G_{A_{k}B}}} \right)^{- 1}\end{bmatrix},$

The coefficients P_(UpAkAk) and P_(UpAkB) are used for vectoring thenon-premium lines in the subblock A_(k) and are the same coefficientsused in NOI in the upstream. Therefore, the coefficients P_(UpAkAk) andP_(UpAkB) do not require any additional memory because they are alreadystored in the memory 140 for NOI in the upstream. Using the coefficientsP_(UpAkAk) and P_(UpAkB) results in a partially vectored rate for linesin subblock A_(k). The remaining coefficients −(G_(BB)−G_(BA) _(k) G_(A)_(k) _(A) _(k) ⁻¹G_(A) _(k) _(B))⁻¹G_(BA) _(k) G_(A) _(k) _(A) _(k) and(G_(BB)−G_(BA) _(k) G_(A) _(k) _(A) _(k) ⁻¹G_(A) _(k) _(B))⁻¹ arespecific to subblock A_(k) and are computed by the controller 130 toensure that the lines in the set of lines B achieve full SNRperformance.

In the case of upstream, the coefficients −(G_(BB)−G_(BA) _(k) G_(A)_(k) _(A) _(k) ⁻¹G_(A) _(k) _(B))⁻¹G_(BA) _(k) G_(A) _(k) _(A) _(k) ⁻¹and (G_(BB)−G_(BA) _(k) G_(A) _(k) _(A) _(k) G_(A) _(k) _(B)) arecorresponding rows of the ideal zero-forcing postcoder for the case thatlines {A_(k),B} are active.

Using the combination {Ak,B} during DOI results in a channel afterpostcoding as:

${{P_{Up}\lbrack k\rbrack}G} = {\quad{\left\lbrack \begin{matrix}0 & 0 & 0 \\0 & P_{{Up}_{A_{k}A_{k}}} & P_{{Up}_{A_{k}B}} \\0 & {{- \begin{pmatrix}{G_{BB} -} \\{G_{{BA}_{k}}G_{A_{k}A_{k}}^{- 1}G_{A_{k}B}}\end{pmatrix}^{- 1}}G_{BA}G_{A_{k}A_{k}}^{- 1}} & \begin{pmatrix}{G_{BB} -} \\{G_{{BA}_{k}}G_{A_{k}A_{k}}^{- 1}G_{A_{k}B}}\end{pmatrix}^{- 1}\end{matrix} \right\rbrack {\quad{\left\lbrack \begin{bmatrix}G_{DD} & G_{{DA}_{k}} & G_{DB} \\G_{A_{k}D} & G_{A_{k}A_{k}} & G_{A_{k}B} \\G_{BD} & G_{{BA}_{k}} & G_{BB}\end{bmatrix} \right\rbrack = \begin{bmatrix}0 & 0 & 0 \\X_{A_{k}D} & {I + Y_{A_{k}A_{k}}} & Y_{A_{k}B} \\X_{BD} & 0 & I\end{bmatrix}}}}}$

where Y_(AkAk), Y_(AkB) are matrix subblocks indicating second ordercrosstalk terms (e.g. terms generated from the product of off-diagonalcrosstalk elements), while X_(AD), X_(BD) are subblocks indicating firstorder crosstalk terms, and P_(Up)[k] is the matrix being used by thepostcoder 410 when {B,A_(k)} is active.

The first order crosstalk terms can be ignored by virtue of the factthat the discontinued lines D transmit no power. The second order termsY_(AA), Y_(AB) cause the lines in A_(k) to operate with “partiallyvectored” performance (better than non-vectored), with first crosstalkterms removed, but second-order terms remaining.

The following description illustrates how memory is saved. P_(Up)[−1] isan NOI postcoder and P_(Up)[k] is a postcoder in use when {B,A_(k)} isactive. P_(Up)[0] is a postcoder in use when the subset B is active.Since

P _(UpAkAk) [k]=P _(UpAkAk)[−1], and

P _(UpAkB) [k]=P _(UpAkB)[−1],

the controller 130 and the memory 140 does not use any additionalstorage beyond P_(Up)[−1] for the P_(UpAkAk)[k] and P_(UpAkB)[k]submatrices of P_(Up)[k].

The controller 130 (e.g., the VCE 280) computes and stores

P _(UpBA) _(k) [k]=−(G _(BB) −G _(BA) _(k) G _(A) _(k) _(A) _(k) ⁻¹ G_(A) _(k) _(B))⁻¹ G _(BA) _(k) G _(A) _(k) _(A) _(k) ⁻¹, and

P _(UpBB) [k]=(G _(BB) −G _(BA) _(k) G _(A) _(k) _(A) _(k) G _(A) _(k)_(B))⁻¹,

which are |B|×|A_(k)| and |B|×|B| matrices, respectively. By contrast,for block TDMA, the controller 130 would have to store the entire(|B|+|A_(k)|)×(|B|+|A_(k)|) matrix P_(Up)[k].

The controller 130 may store the |B|×|B| matrix

P _(UpBB)[0]=G _(BB) ⁻¹

for when only the premium lines B are active.

In terms of matrix inversions, the controller 130 inverts a |B|×|B|matrix G_(BB)−G_(BA) _(k) G_(A) _(k) _(A) _(k) ⁻¹G_(A) _(k) _(B) and a(|A_(k)|)×(|A_(k)|) matrix G_(A) _(k) _(A) _(k) . Sequentially, the VCE280 computes G_(A) _(k) _(A) _(k) ⁻¹, then does matrix multiplicationsand subtraction to obtain G_(BB)−G_(BA) _(k) G_(A) _(k) _(A) _(k)⁻¹G_(A) _(k) _(B). The VCE 280 then calculates (G_(BB)−G_(BA) _(k) G_(A)_(k) _(A) _(k) ⁻¹G_(A) _(k) _(B))⁻¹.

In another example embodiment, the controller 130 uses the followingpostcoder coefficients in DOI when the set of lines {A_(k), B} areactive:

$\begin{bmatrix}P_{{Up}_{A_{k}A_{k}}} & {{- P_{{Up}_{A_{k}A_{k}}}}G_{A_{k}B}G_{BB}^{- 1}} \\P_{{Up}_{{BA}_{k}}} & {\left( {I - {P_{{Up}_{{BA}_{k}}}G_{A_{k}B}}} \right)G_{BB}^{- 1}}\end{bmatrix},$

The coefficients P_(UpAkAk) and P_(UpBAk) are used for reducingcrosstalk from the non-premium lines in the subblock A_(k) intonon-premium and premium lines, respectively, and are the samecoefficients used in NOI. Therefore, the coefficients P_(UpAkAk) andP_(UpBAk) do not require any additional memory because they are alreadystored in the memory 140 for NOI. Using the coefficients P_(UpAkAk) andP_(UpBAk) results in partially reduced crosstalk from lines in subblockA_(k). The remaining coefficients −P_(Up A) _(k) _(A) _(k) G_(A) _(k)_(B)G_(BB) ⁻¹ (I−P_(Up BA) _(k) G_(A) _(k) _(B))G_(BB) ⁻¹ are specificto subblock A_(k) and are computed by the controller 130 to ensure thatthe lines in the set of lines B do not generate any crosstalk amongthemselves or into the lines in A_(k). In conjunction with power controlon the lines in A_(k), this can allow the lines in B to achieve full SNRperformance. For power control, the controller 130 may communicate tothe CPEs 200-1-200-m in the set A_(k) a reduced transmit power level touse. The CPEs 200-1-200-m will then transmit at the reduced power level.

Using the combination {Ak,B} during DOI results in a channel afterpostcoding as:

${{P_{Up}\lbrack k\rbrack}G} = {\begin{bmatrix}0 & 0 & 0 \\0 & P_{{Up}_{A_{k}A_{k}}} & {{- P_{{Up}_{A_{k}A_{k}}}}G_{A_{k}B}G_{BB}^{- 1}} \\0 & P_{{Up}_{{BA}_{k}}} & {\left( {I - {P_{{Up}_{{BA}_{k}}}G_{A_{k}B}}} \right)G_{BB}^{- 1}}\end{bmatrix}{\quad{\left\lbrack \begin{bmatrix}G_{DD} & G_{{DA}_{k}} & G_{DB} \\G_{A_{k}D} & G_{A_{k}A_{k}} & G_{A_{k}B} \\G_{BD} & G_{{BA}_{k}} & G_{BB}\end{bmatrix} \right\rbrack = \begin{bmatrix}0 & 0 & 0 \\X_{A_{k}D} & {I + Y_{A_{k}A_{k}}} & 0 \\X_{BD} & Y_{{BA}_{k}} & I\end{bmatrix}}}}$

where Y_(AkAk), Y_(BkAk) are matrix subblocks indicating second ordercrosstalk terms (e.g. terms generated from the product of off-diagonalcrosstalk elements), and X_(AkD), X_(BD) are matrix subblocks indicatingfirst order crosstalk terms. The first order crosstalk terms can beignored by virtue of the fact that the discontinued lines D transmit nopower. Moreover, the controller 130 may reduce the transmit power of thelines in A_(k) until an interference caused to the premium lines byY_(BAk) is negligible (i.e., below the noise floor for lines in B).

In the upstream, this choice of subblock {A_(k),B} depends on theinstantaneous traffic load requirements.

Only the rightmost subblocks −P_(UP A) _(k) _(A) _(k) G_(A) _(k)_(B)G_(BB) ⁻¹ and (I−P_(UP BA) _(k) G_(A) _(k) _(B))G_(BB) ⁻¹ areadditionally stored and computed for DOI (coefficients are also storedfor NOI). The rightmost subblocks −P_(Up A) _(k) _(A) _(k) G_(A) _(k)_(B)G_(BB) ⁻¹ and (I−P_(Up BA) _(k) G_(A) _(k) _(B))G_(BB) ⁻¹ correspondto a (|B|+|A_(k)|)×|B| matrix, whereas for block TDMA the same subblockwould correspond to a (|B|+|A_(k)|)×(|B|+|A_(k)|) matrix to be stored.In terms of matrix inversions, the controller 130 computes a |B|×|B|matrix inverse G_(BB) ⁻¹), versus (|A_(k)|+|B|)×(|A_(k)|+|B|) matrixinverses required for block TDMA.

This saves on memory and computational complexity while allowing premiumservice for a subset of lines and discontinuable operation for theremaining lines, based on the traffic load or on operator/systemrequirements (e.g., minimum data rates associated with the lines). Inparticular, the discontinued lines D can save on power consumption.

FIG. 5A illustrates a method of using block boosting on the upstreamaccording to an example embodiment. The method of FIG. 5A may beperformed by the access node 100. More specifically, the controller 130may perform steps S300-S320.

At S500, the access node obtains a received signal vector over a firstset of lines and a second set of lines. The first set of lines may bethe set of lines B and the second set of lines may be the set of linesA_(k).

At S505, the controller 130 obtains NOI postcoder coefficients for thesecond set of lines. For example, the controller 130 obtains thecoefficients P_(UpAkAk) and P_(UpBAk) used in NOI for the upstream fromthe memory 140. In another example, the coefficients P_(UpAkB) areobtained instead of the coefficients P_(UpBAk).

At S510, the controller 130 determines DOI postcoder coefficients forthe first set of lines. The DOI postcoder coefficients for the first setof lines and the NOI postcoder coefficients for the second set of linesform part of a postcoding matrix. Moreover, in an example embodiment,the controller 130 may communicate to the CPEs 200-1-200-m in the setA_(k) a reduced transmit power level to use. The CPEs 200-1-200-m willthen transmit at the reduced power level.

At S515, the controller 130 postcodes a received signal vector from theCPEs 200-1-200-m to the processing devices 125-1-125-m for adiscontinuous operation interval using the postcoding matrix. At S520,the controller 130 sends the postcoded signal vector to the associatedprocessing devices 125-1-125-m. More specifically, the received signalvector comes from 125-1-125-m and then the postcoded signal vector issent back to 125-1-125-m. The signals originally came from the CPEs,came through the cable, through analog-to-digital circuits (ADC)(line-drivers 135-1-135-m) and into the processing units 125-1-125-m.

Upstream—Sequential Boosting

As an alternative to block boosting in the upstream, the controller 130may implement sequential boosting for the upstream (postcoder), in atleast some example embodiments.

When using sequential boosting for the upstream, the controller 130sequentially applies two sparse matrices as follows:

${\begin{bmatrix}0 & 0 & 0 \\0 & P_{{Up}_{AA}} & 0 \\0 & P_{{Up}_{BA}} & I\end{bmatrix}\begin{bmatrix}0 & 0 & {{- G_{DB}}G_{BB}^{- 1}} \\0 & I & {{- G_{AB}}G_{BB}^{- 1}} \\0 & 0 & G_{BB}^{- 1}\end{bmatrix}},$

The controller 130 does not identify subblocks A_(k) in advance, but anylines outside the premium set of lines can discontinue at all moments,and constitute the non-premium lines A. The computations performed bythe controller 130 are sequential, meaning that the results of the firstmatrix multiplication (the matrix with the G and G−1 terms) must becalculated and available before beginning the second matrixmultiplication (matrix with the P_(Up) terms). To get full performanceon the premium lines B, the transmit power is also reduced for the linesin A.

FIG. 5B illustrates a method of using sequential boosting on theupstream according to an example embodiment. The method of FIG. 5B maybe performed by the access node 100. More specifically, the controller130 may perform steps S550-S570.

At S550, the controller 130 determines a first matrix for precodingtransmission from an access node to a plurality of downstream devicesover a plurality of lines. The plurality of lines includes first linesand second lines. The first lines are associated with a higher vectoringperformance than the second set of lines. For example, the first linesmay be the set of lines B and the second lines may be the set of linesA_(k). The first matrix includes an identity matrix and a |B|×|B|inverse channel submatrix G_(BB) ⁻¹ where |B| is the number of firstlines. The first matrix also includes −G_(DB)G_(BB) ⁻¹ and −G_(AB)G_(BB)⁻¹ submatrices.

At S560, the controller 130 determines a second matrix for precoding thetransmission. The second matrix includes normal operation interval (NOI)postcoding coefficients (e.g., P_(UpAA) and P_(UpBA)) associated withthe first and second lines and an identity matrix. At S570, thecontroller 130 postcodes a signal by sequentially applying the firstmatrix followed by the second matrix to the signal vector. Moreover, inan example embodiment, the controller 130 may determine a reducedtransmit power level to use for the lines in the set A_(k). The CPEs200-1-200-m will then transmit at the reduced power level.

Example embodiments being thus described, it will be obvious that thesame may be varied in many ways. Such variations are not to be regardedas a departure from the spirit and scope of example embodiments, and allsuch modifications as would be obvious to one skilled in the art areintended to be included within the scope of the claims.

We claim:
 1. A method comprising: determining a first set of lines and asecond set of lines in a system; obtaining signals to be transmittedover, or received from, the first set of lines and the second set oflines; obtaining normal operation interval (NOI) vectoring coefficientsfor the second set of lines; determining discontinuous operationinterval (DOI) vectoring coefficients for the first set of lines, theDOI vectoring coefficients for the first set of lines and the NOIvectoring coefficients for the second set of lines being part of avectoring matrix; and jointly processing the signals for a discontinuousoperation interval using the vectoring matrix.
 2. The method of claim 1,wherein the vectoring matrix includes a |B|×(|B|+|A|) submatrix for thediscontinuous operation interval, where |B| is a number of the first setof lines corresponding to the DOI vectoring coefficients and |A| is anumber of the second set of lines corresponding to the NOI vectoringcoefficients.
 3. The method of claim 2, further comprising: storing the|B|×(|B|+|A|) submatrix in a memory storage medium.
 4. The method ofclaim 1, wherein the first set of lines is associated with a highervectoring performance than the second set of lines.
 5. The method ofclaim 1, wherein the determining determines the first and second sets oflines based on at least one of a traffic load of the system and staticdata rate values associated with the lines in the first and second setsof lines, respectively.
 6. The method of claim 1, wherein the NOIvectoring coefficients and the DOI vectoring coefficients are precodercoefficients and the vectoring matrix is a precoding matrix.
 7. Themethod of claim 1, wherein the NOI vectoring coefficients and the DOIvectoring coefficients are postcoder coefficients and the vectoringmatrix is a postcoding matrix.
 8. The method of claim 7, wherein thepostcoding matrix includes a (|B|+|A|)×|B| submatrix for thediscontinuous operation interval, where |B| is a number of the first setof lines corresponding to the DOI postcoder coefficients and |A| is anumber of the second set of lines corresponding to the NOI postcodercoefficients.
 9. The method of claim 8, further comprising: storing the(|B|+|A|)×|B| submatrix in a memory storage medium.
 10. A methodcomprising: determining a first set of lines and a second set of linesin a system; obtaining signals to be transmitted over, or received from,the first set of lines and the second set of lines; determining a firstvectoring matrix for the first set of lines and the second set of lines,the first vectoring matrix including an identity matrix and a |B|×|B|inverse channel matrix, where |B| is a number of the first set of lines;determining a second vectoring matrix, the second vectoring matrixincluding normal operation interval (NOI) vectoring coefficientsassociated with the first set of lines and the second set of lines andan identity matrix; and jointly processing the signals for adiscontinuous operation interval by sequentially applying the firstmatrix and the second matrix.
 11. The method of claim 10, wherein thejointly processing jointly processes the signals by sequentiallyapplying the second matrix followed by the first matrix.
 12. The methodof claim 10, wherein the jointly processing jointly processes thesignals by sequentially applying the first matrix followed by the secondmatrix.
 13. The method of claim 10, wherein the first set of lines isassociated with a higher vectoring performance than the second set oflines.
 14. An access node comprising: a processor configured to,determine a first set of lines and a second set of lines in a system;obtain signals to be transmitted over, or received from, the first setof lines and the second set of lines; obtain normal operation interval(NOI) vectoring coefficients for the second set of lines; determinediscontinuous operation interval (DOI) vectoring coefficients for thefirst set of lines, the DOI vectoring coefficients for the first set oflines and the NOI vectoring coefficients for the second set of linesbeing part of a vectoring matrix; and jointly process the signals for adiscontinuous operation interval using the vectoring matrix.
 15. Theaccess node of claim 14, wherein the vectoring matrix includes a|B|×(|B|+|A|) submatrix for the discontinuous operation interval, where|B| is a number of the first set of lines corresponding to the DOIvectoring coefficients and |A| is a number of the second set of linescorresponding to the NOI vectoring coefficients.
 16. The access node ofclaim 15, wherein the processor is configured to store the |B|×(|B|+|A|)submatrix in a memory storage medium.
 17. The access node of claim 14,wherein the first set of lines is associated with a higher vectoringperformance than the second set of lines.
 18. The access node of claim14, wherein the processor is configured to determine the first andsecond sets of lines based on at least one of a traffic load of thesystem and static data rate values associated with the lines in thefirst and second sets of lines, respectively.
 19. The access node ofclaim 14, wherein the NOI vectoring coefficients and the DOI vectoringcoefficients are precoder coefficients and the vectoring matrix is aprecoding matrix.
 20. The access node of claim 14, wherein the NOIvectoring coefficients and the DOI vectoring coefficients are postcodercoefficients and the vectoring matrix is a postcoding matrix.
 21. Theaccess node of claim 20, wherein the postcoding matrix includes a(|B|+|A|)×|B| submatrix for the discontinuous operation interval, where|B| is a number of the first set of lines corresponding to the DOIpostcoder coefficients and |A| is a number of the second set of linescorresponding to the NOI postcoder coefficients.
 22. The access node ofclaim 21, the processor is configured to store the (|B|+|A|)×|B|submatrix in a memory storage medium.
 23. An access node comprising: aprocessor configured to, determine a first set of lines and a second setof lines in a system; obtain signals to be transmitted over, or receivedfrom, the first set of lines and the second set of lines; determine afirst vectoring matrix for the first set of lines and the second set oflines, the first vectoring matrix including an identity matrix and a|B|×|B| inverse channel matrix, where |B| is a number of the first setof lines; determine a second vectoring matrix, the second vectoringmatrix including normal operation interval (NOI) vectoring coefficientsassociated with the first set of lines and the second set of lines andan identity matrix; and jointly process the signals for a discontinuousoperation interval by sequentially applying the first matrix and thesecond matrix.
 24. The access node of claim 24, wherein the processor isconfigured to jointly process the signals by sequentially applying thesecond matrix followed by the first matrix.
 25. The access node of claim24, wherein the processor is configured to jointly process the signalsby sequentially applying the first matrix followed by the second matrix.